Signal Integrity (SI)

It is vital to consider SI from the initial stages of design. Before starting concrete design, we optimize the topology, terminals, and load.


As the device speed increases, it becomes unfeasible to design a printed board that will operate using past experience and intuition alone. Conducting a pre-simulation at the initial stage of design will make it possible to identify and remedy issues beforehand.


Smoothly perform arrangement and wiring without repeated work through the global optimization of each parameter, including layout of main components, number of loads, driver capacity, and wiring topology. This makes it possible to shorten design time and reduce the number of prototypes.

Analysis services

  • Topology optimization (wiring length, branch positions, wiring paths)
  • Optimization of terminal conditions
  • Driver selection (drive capability, any options, etc.)
  • Others
  • Crosstalk analysis
  • Checking for skew
  • Others
Defect analysis
  • We reproduce bad waveforms on actual device, investigate, and propose remedies.

Sample analysis

100 MHz clock: Sample analysis of signals between clock buffer and SDRAM